VHDL中attribute string of signal: signal is "NO";How do I keep Xilinx XST from merging nets from my design?

How do I keep Xilinx XST from merging nets from my design?

I'm asking and answering this question so that I can find it again in the future...

How do I keep XST from merging two logically equivalent nets into one (which normally is a good idea to save resources, but may not be a good idea from a timing view)?

I have a design with 2 counters that are driven by the same clk. XST merged the lowest bit of the counters into one counter, but this is a problem, because the counters need to be separated in the design due to IOB placement constraints. I need the counters (specifically the lowest bit of the counter) to be distinct.

 

Answer:

you need to set 2 constraints on the net in your RTL. Check the synthesis report for your net to make sure that XST did what you wanted.

In Verilog

复制代码(* equivalent_register_removal="no" *) (* keep="true" *) reg signal_name ;

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(* equivalent_register_removal="no" *)
(* keep="true" *)
reg  signal_name ;

In VHDL

复制代码attribute equivalent_register_removal: string; attribute equivalent_register_removal of signal_name : signal is "no"; attribute keep:string; attribute keep of signal_name :signal is "true"; Your signal_name : std_logic;The link: http://stackoverflow.com/questions/11125142/how-do-i-keep-xilinx-xst-from-merging-nets-from-my-designMade by Tim.

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attribute equivalent_register_removal: string;   
attribute equivalent_register_removal of signal_name : signal is "no";
attribute keep:string;
attribute keep of signal_name :signal is "true";
Your signal_name  : std_logic;

The link: http://stackoverflow.com/questions/11125142/how-do-i-keep-xilinx-xst-from-merging-nets-from-my-design


Made by Tim.