Slicer/DCVS simulation - metastability 动态比较器的亚稳态仿真

以前工作的上网机没有中文输入法，再用中文写一遍

1, Dynamic latch comparator (slicer), rather than the traditional continuous time comparator, uses the "metastability" instead of "gain" or "bandwidth" to characterize the circuit design. [1]

和放大器/连续比较器不一样，动态比较器使用“metastability”来衡量(某速度下的)增益和带宽。

2, To simulate the metastability, apply a small voltage (~10uV) to the slicer input, then toggle the clk to let the slicer sense. Then the output voltage waveform is monitored and the time for the waveform to change from latching node Vx=V1=1x to Vx=V2=2.718x(the constant 'e') is measured. (Vx=1x, e.g., Vx=10uV as an arbitrary small voltage, any small voltage is OK)

要仿真亚稳态，在slicer的输入端给一个小输入，然后把CLK振起来让比较器采样。监测输出电压波形，记录下输出电压从一个值变化到另一个更大值的时间，比如从10uV变化到27.18uV。

3, The time from Vx=1x to Vx=2.718x is labeled as tm. tm is a method to characterize the regeneration time constant of the slicer.

刚刚记录下来的时间可以叫做tm，tm可以表征slicer的regerneration时间。

From the time constant, the error probability (bit error rate) of the slicer can be figured out by following formula:

用tm可以计算出ADC的出错概率，公式如下

Perror = (2 * VL) * exp(-T / tm) / ( AUL * Q)  ["Comparator Metastability Analysis", William Evans, Eric Naviasky, Hao Tang...]

of which,

VL is the minimum valid logic level the comparator must generate in Volts, e.g: 0.8vdd = 0.96V for vdd=1.2V (doubts...??minimum CMOS voltage?) VL是电路工作所需要的最小逻辑电平

AUL is the comparator's unlatched gain in V/V, for a strong arm latch without pre-amp, AUL=1

对于strong arm的slicer，认为AUL=1

Q is the quantum size at the slicer input in Volts. For a 10bit ADC, Q=(vrefp-vrefn)/1024 = 0.8V/1024 = 780uV Q是ADC一个code step对应的电压大小，寓意slicer所能看到的最小输入电压；对于NRZ的rx，我觉得应该可以类比为1bit的ADC，Q应该是评估出的slicer输入端看到的最小眼高，如果带eye monitor，那么应该是eye monitor的最小step；Q的绝对值应该不是那么重要，主要看相对值

T is the max time for slicer to make a decision in seconds. -> half tck used to trigger slicer.

T是slicer用来采样判决的时间，理想情况下应该是一半的采样周期

4, Use pss (periodic steady state) analysis to simulate mestability of slicer. The Spectre RF shooting newton (pss) engine is the primary analysis  used to characterize the dynamic comparator by obtain the periodic steady-state operating points （就类似连续电路里的DC分析）.  In addition from the periodic steady state, the circuit can be linearized and small signal analysis performed. The periodic steady state small-signal analysis is used for other comparator measurements, for example, noise. Shooting Newton analysis for the dynamic comparator uses the frequencies defined in the sources in the test bench. Transient noise can also be used for simulating comparator metastability.

Metastability is more like a  parameter of bandwidth -> gain vs frequency. So, spec gives a metastability, calculation/simulation yields a curve of metastabiliby vs. design size(gain, speed) and parasitic cap.

[1] Cadence 2014 ADC Verification Workshop

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