【FPGA基础】常见易错点积累
1、# ** Error: …/…/code/Rtl/send_to_lvds_n.v(167): A begin/end block was found with an empty body. This is permitted in SystemVerilog, but not permitted in Verilog. Please look for any stray semicolons.问题原因：代码中多了一个“;”2、使用仿真模型时，如果在某个testbench文件中使用到了该
