Verilog代码BCD计数器
设计代码`timescale 1ns / 1psmodule Test0953(clk,reset,count);input clk;input reset;output [3:0] count;reg [3:0] count;parameter zero=0,one=1,two=2,three=3,four=4,five=5,six=6,seven=7,eight=8,nine=9;reg [3:0] pr_state,nx_state;/////////////////////////
