ISE 错误总结 （不定时更新）

学习当中遇到的一些总结，4,5,6是参考的大神的博客的解决办法：

1.ERROR:HDLCompiler:1511 - "D:ise excrccrc_testcrc_test.v" Line 82: Mix of blocking and non-blocking assignments to variable <crc_end> is not a recommended coding practice.

阻塞与非阻塞赋值一起使用了

2.ERROR：Non-net port data_in cannot be of mode input

输入不可以使用input reg

3.Assignment under multiple single edges is not supported for synthesis

ISE综合时出错，在多个单边的分配不支持的合成。

4.在Translate过程中出现如下错误：

"ERROR:ConstraintSystem:59 - Constraint< xxx >: NET/INST "xxx" 未找到。Please verify that:1.The specified design element actually exists in the design.The specified object is spelled correctly in the constraint source file."

解决办法：为了防止综合工具删除 net，应为 net 应用 "KEEP"

例如：(* KEEP = "TRUE" *)  wire  [3:0] SdData_o ;

另外注意检查管脚约束UCF文件中，是否有对多余的IO信号分配了同一个管脚

5、在implement时点击translate后，出现如下错误：

(转载)ERROR:NgdBuild:924- input pad net 'clk' is driving non-buffer primitive。

意为输 入信号clk未经buffer就用来驱动其他primitives了

主要的原因：

输入时钟clk_in在作为DCM输入引脚的时候又为其他module的输入，也就是说clk有两个load，连接PLL时，输入信号先要连接到内部buffer以产生较强的驱动能力，从而保证时钟的时 序质量。但是由于输入信号的另一分支不经过任何电路就直接连接到了输出Pad ，所以存在一种可能，即连接buffer的分支会被短路，从而失去预期的效果。即输入clk两个分支，一个直接连到模块fsm；一个连在了DCM的输入时钟源。由于经过DCM时会自动加一个buffer缓冲器，而到fsm会直接连在一起，这样会造成DCM这一路短路出现错误。正因为如此，ISE给出了错误警告。

解决办法：clk只是连接一个load，就是DCM。DCM两个输出一个CLKFX_OUT_1，另外一个用CLK0_OUT，此信号和clk无论相位还是频率是一样的。

另外： chipscope 不能用晶振输入时钟来作为采样时钟

PLL的时候，又遇到PLL倍频输出的时钟不能直接连接到普通IO的问题。要命的是，板子上的DSP需要FPGA给出主时钟才能运行，硬件这样做好了，DSP要能工作，时钟必须要从那个引脚输出。刚开始，PLL的时钟直接连接到IO，map失败，一看原因，迫不及待在ucf文件中加入下面的约束：

PIN "U_CLOCK_PLL/clkout1_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
PIN "U_CLOCK_PLL/clkout2_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;

    map的时候生成下面的警告。虽然得到了下载文件，尝试了几次，DSP连不上。无奈，只有按照ISE给出的建议：

WARNING:Place:1205 - This design contains a global buffer instance,<U_CLOCK_PLL/clkout2_buf>, driving the net, <dsp_clkin_OBUF>, that is driving the following (first 30) non-clock source pins off chip.
< PIN: dsp_clkin.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution:

instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to.C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <U_CLOCK_PLL/clkout2_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.

WARNING:Place:1205 - This design contains a global buffer instance, <U_CLOCK_PLL/clkout1_buf>, driving the net, <dsp_aeclkin_OBUF>, that is driving the following (first 30) non-clock source pins off chip.
< PIN: dsp_aeclkin.O; >
This design practice, in Spartan-6, can lead to an unroutable situation due to limitations in the global routing. If the design does route there may be excessive delay or skew on this net. It is recommended to use a Clock Forwarding technique to create a reliable and repeatable low skew solution:

instantiate an ODDR2 component; tie the .D0 pin to Logic1; tie the .D1 pin to Logic0; tie the clock net to be forwarded to .C0; tie the inverted clock to.C1. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <U_CLOCK_PLL/clkout1_buf.O> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.


    按照其中的说法：实例化一个ODDR2，这个小元件的详细介绍在xilinx参考文档ug381中有详细介绍。实例化的代码：

ODDR2 #(
.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
.INIT(1'b0), // Sets initial state of the Q output to 1'b0 or 1'b1
.SRTYPE("SYNC") // Specifies "SYNC" or "ASYNC" set/reset
) U_ODDR2_XXXHZ
(
.Q(oddr2_xxxmhz), // 1-bit DDR output data
.C0(clock_xxxmhz), // 1-bit clock input
.C1(~clock_xxxmhz), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D0(1'b1), // 1-bit data input (associated with C0)
.D1(1'b0), // 1-bit data input (associated with C1)
.R(1'b0), // 1-bit reset input
.S(1'b0) // 1-bit set input
);

信号oddr2_xxxmhz就是那个可以输出到普通IO的信号了。

6.<CLK75MhZ/clkout1_buf>, driving the net, <CLKOUT_OBUF>, that is driving the following (first 30) non-clock source pins off chip.
    CLK75MhZ/clkout1_buf是全局时钟布线，驱动一个向外输出的时钟引脚，因为 该输出时钟引用啦全局时钟布线，故会选择芯片专用时钟输出引脚进行适配，如果这个被分配的引脚是普通IO就会造成适配失败。
可以把这个时钟改到专用时钟引脚，也可以不用全局时钟走线。 If you wish to override this recommendation, you may use the CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote this message to a WARNING and allow your design to continue.
在UCF文件中加入：NET "CLK75MhZ" CLOCK_DEDICATED_ROUTE = FALSE 不使用全局时钟布线。

7.Thedual data rate register "gen_do[0].do_oddr" failed to  join an OLOGIC component as required.

Thedual data rate register "gen_do[1].do_oddr" failed to  join an OLOGIC component as required.

…

Thedual data rate register "gen_do[31].do_oddr" failed to  join an OLOGIC component as required.

错误的原因是ODDR的输出必须直接连到输出pad上，不可以再引进逻辑内部。因此会出现do_oddr的输出无法连入OLOGIC中。

8.Port connections cannot be mixed ordered and named

翻译：端口连接不能混合命令和命名

example ：

Myclock1 c2(
.clk(clk),
.clk1(clk2),
);

原因：调用module的时候最后一个端口后面多了一个逗号。

最后

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