7 Physical Layer 物理层7.1 D-PHY Physical Layer Option

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我是靠谱客的博主端庄荔枝，最近开发中收集的这篇文章主要介绍7 Physical Layer 物理层7.1 D-PHY Physical Layer Option，觉得挺不错的，现在分享给大家，希望可以做个参考。

概述

The CSI-2 lane management layer interfaces with the D-PHY and/or C-PHY physical layers described in [MIPI01] and [MIPI02], respectively. A device shall implement either the C-PHY 1.2 or the D-PHY 2.1physical layer and may implement both. A practical constraint is that the PHY technologies used at both ends of the Link need to match: a D-PHY transmitter cannot operate with a C-PHY receiver, or vice versa.
CSI-2 lane management layer分别与[MIPI01]和[MIPI02]中描述的D-PHY或C-PHY物理层进行接口。设备应实现C-PHY 1.2或D-PHY 2.1物理层，或者两个都实现。一个实际的约束是，链路两端使用的PHY技术需要匹配:D-PHY发射器不能operate C-PHY接收器，反之亦然。

7.1 D-PHY Physical Layer Option

The D-PHY physical layer for a CSI-2 implementation is composed of a number of unidirectional data Lanes and one clock Lane. All CSI-2 transmitters and receivers implementing the D-PHY physical layer shall support continuous clock behavior on the Clock Lane, and optionally may support non-continuous clock behavior.
For continuous clock behavior the Clock Lane remains in high-speed mode, generating active clock signals between the transmission of data packets.
For non-continuous clock behavior the Clock Lane enters the LP-11 state between the transmission of data packets.
The minimum D-PHY physical layer requirement for a CSI-2 transmitter is

Data Lane Module: Unidirectional master, HS-TX, LP-TX and a CIL-MFEN function
Clock Lane Module: Unidirectional master, HS-TX, LP-TX and a CIL-MCNN function

The minimum D-PHY physical layer requirement for a CSI-2 receiver is

Data Lane Module: Unidirectional slave, HS-RX, LP-RX, and a CIL-SFEN function
Clock Lane Module: Unidirectional slave, HS-RX, LP-RX, and a CIL-SCNN function

All CSI-2 implementations supporting the D-PHY physical layer option shall support forward escape ULPS on all D-PHY Data Lanes.
To enable higher data rates and higher number of lanes the physical layer described in [MIPI01] includes an independent deskew mechanism in the Receive Data Lane Module. To facilitate deskew calibration at the receiver the transmitter Data Lane Module provides a deskew sequence pattern.
Since deskew calibration is only valid at a given transmit frequency:
For initial calibration sequence the Transmitter shall be programmed with the desired frequency for calibration. It will then transmit the deskew calibration pattern and the Receiver will autonomously detect this pattern and tune the deskew function to achieve optimum performance.
For any transmitter frequency changes the deskew calibration shall be rerun.
Some transmitters and/or receivers may require deskew calibration to be rerun periodically and it is suggested that it can be optimally done within vertical or frame blanking periods.
For low transmit frequencies or when a receiver described in [MIPI01] is paired with a previous version transmitter not supporting the deskew calibration pattern the receiver may be instructed to bypass the deskew mechanism.
The D-PHY v2.1 physical layer [MIPI05] provides Alternate Low Power State (ALPS) using Low Voltage Low Power (LVLP) signaling, which may optionally replace the legacy Low Power State (LPS). Use of LVLP can help alleviate current leakage and electrical overstress issues with image sensors and applications processors.

7.1 D-PHY物理层选项

用于CSI-2实现的D-PHY物理层由许多单向数据通道和一个时钟通道组成。所有实现D-PHY物理层的CSI-2发射器和接收器都应支持时钟通道上的连续时钟行为，也可以支持非连续时钟行为。
对于连续的时钟行为，时钟通道保持在高速模式，在数据包传输之间产生主动的时钟信号。
对于非连续的时钟行为，时钟通道在数据包传输之间进入LP-11状态。

CSI-2发射机的最小D-PHY物理层要求是

数据通道模块:单向主控，HS-TX, LP-TX和一个CIL-MFEN功能
时钟通道模块: 单向主控，HS-TX, LP-TX和CIL-MCNN功能

CSI-2接收机的最小D-PHY物理层要求是

数据通道模块:单向从机、HS-RX、LP-RX、CIL-SFEN功能
时钟通道模块:单向从机，HS-RX, LP-RX，和一个CIL-SCNN功能

所有支持D-PHY物理层选项的CSI-2实现应在所有D-PHY数据通道上支持前向推迟 ULPS。
为了启用更高的数据速率和更高的通道数，在[MIPI01]中描述的物理层在接收数据通道模块中包括一个独立的deskew mechanism。为了便于在接收端进行deskew校准，发射机数据通道模块提供了deskew sequence pattern。
由于deskew校准只在给定的发射频率下有效:
对于初始校准序列，Transmitter应按校准所需的频率进行编程。然后，它将发送deskew校准模式和接收器将自动检测这一模式，并调整deskew function，以实现最佳性能。
当Transmitter频率发生变化时，应重新进行deskew校准。
一些Transmitter或receivers可能需要周期性地重新进行deskew校准，建议在垂直或帧落料周期内进行校准。
对于低发射频率或当[MIPI01]中描述的接收器与不支持deskew校准模式的先前版本发射机配对时，可以指示接收器绕过deskew机制。
D-PHY v2.1物理层[MIPI05]使用低电压低功率(LVLP)信令提供Alternate Low Power State (ALPS)，可以选择性地替代传统的低功率状态(LPS)。使用LVLP可以帮助缓解图像传感器和应用处理器的电流泄漏和电应力过大问题。

7.1.1 D-PHY v2.1 Compatibility with D-PHY v2.0 (Informative)

A D-PHY v2.0 [MIPI05] or earlier physical layer and a D-PHY v2.1 physical layer are fully interoperable.
For bit rates above 2.5 Gbps per Lane, a D-PHY v2.0 [MIPI05] or earlier physical layer and a D-PHY v2.1 physical layer are fully interoperable, provided certain new D-PHY v2.1 features are disabled as permitted by the D-PHY v2.1 specification. Such features include the Alternate Calibration Sequence, Preamble Sequence, and Extended Sync pattern as described in Section 6.13 and Section 6.14 of [MIPI01].
These features allow system interfaces to more robustly compensate for variations such as temperature and voltage when operating at bit rates above 2.5 Gbps but are not supported by D-PHY v2.0.

D-PHY v2.0 [MIPI05]或更早的物理层和D-PHY v2.1物理层是完全可互操作的。
对于per Lane 2.5 Gbps以上的比特率，D-PHY v2.0 [MIPI05]或更早的物理层和D-PHY v2.1物理层是完全可互操作的，前提是按照D-PHY v2.1规范允许禁用某些新的D-PHY v2.1特性。这些特性包括备用校准序列、前导序列和扩展同步模式，如[MIPI01]章节6.13和章节6.14所述。
这些特性允许系统接口在比特率高于2.5 Gbps时更健壮地补偿温度和电压等变化，但D-PHY v2.0不支持这些特性。

7.2 C-PHY Physical Layer Option

The C-PHY physical layer for a CSI-2 implementation is composed of one or more unidirectional Lanes.
The minimum C-PHY physical layer requirement for a CSI-2 transmitter Lane module is:
• Unidirectional master, HS-TX, LP-TX and a CIL-MFEN function
• Support for Sync Word insertion during data payload transmission
The minimum C-PHY physical layer requirement for a CSI-2 receiver Lane module is:
• Unidirectional slave, HS-RX, LP-RX, and a CIL-SFEN function
• Support for Sync Word detection during data payload reception 76
All CSI-2 implementations supporting the C-PHY physical layer option shall support forward escape ULPS on all C-PHY Lanes.
The C-PHY Physical Layer provides Alternate Low Power State (ALPS) signaling using Low Voltage Low Power (LVLP) signaling or Alternate Low Power (ALP) Embedded Codes, which may optionally replace the legacy Low Power State (LPS). Use of ALPS can help alleviate current leakage and electrical overstress issues with image sensors and applications processors. ALPS using the ALP Embedded Codes can also help achieve longer reach for CSI-2 imaging interface channels before re-drivers and re-timers become necessary.

CSI-2实现的C-PHY物理层由一个或多个单向通道组成。

CSI-2发射机Lane模块的最小C-PHY物理层要求为:

单向主控，HS-TX, LP-TX和一个CIL-MFEN函数
支持在数据载荷传输期间同步字插入

CSI-2接收机Lane模块的最小C-PHY物理层要求为:

具有单向slave、HS-RX、LP-RX和CIL-SFEN功能
在数据载荷接收期间支持同步字检测

所有支持C-PHY物理层选项的CSI-2实现应在所有C-PHY通道上支持前向推迟 ULPS。
C-PHY物理层提供了Alternate Low Power State (ALPS)信令，使用Low Voltage Low Power (LVLP)信令或Alternate Low Power (ALP) Embedded code，可以选择性地替代传统的Low Power State (LPS)。使用ALPS可以帮助缓解图像传感器和应用处理器的电流泄漏和电应力过大问题。在需要重新驱动和重新定时器之前，使用ALP嵌入式代码的ALPS还可以帮助实现CSI-2成像接口通道到达更远距离。