VCS和Verdi联合仿真编写RTL代码VCS编译Verdi查看波形
编写RTL代码设计文件如下:add.vmodule adder(input clk,input wire [31:0] a,input wire [31:0] b,output reg [31:0] c);always@(posedge clk) c<=a+b;endmodulesub.vmodule suber(input wire clk,input wire [31:0] a,input wire [31:0] b,output reg [3
